公司信息
Responsibilities
-Understanding the expected functionality of designs.
-Designing and developing verification environment
-Improve the verification architecture and flow
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
Qualifications
-MS in CS/ME.
-Minimum of five years’ experience.
-Candidate should be familiar with as System Verilog, UVM verification.
-Candidate should be familiar with industry standard ASIC design and verification tools and flow.
-Candidate should be familiar with basic computer architecture
-Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Requirements
-Verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Independent and self-managing.
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-Familiar with C/C/Java or any ob
-Familiar with UVM source code or key UVM mechanism is a plus
-Has experience of setup over 100K lines verification environment
-Knowledge of DDR protocol is a plus.
-Knowledge of Mixed signal verification is a plus
