soc design verification engineer数字验证

天津恩智浦强芯

岗位描述

Job Description

The position is responsible for developing verification plan, testcase, and verify the functionality MCU/MPU(Coretx-M/A) SOC and reporting the bugs in SOC or IP level.

Responsibilities: 

Verification plan development based Ｏn SOC spec, test case development and improvement to have better coverage and verification quality.

Ensure the complex SoC verification functional coverage and quality for SOC spec cross-check.

Work closely with backend and other function teams Ｏn power/timing analysis at gate level simulation.

Co-work with IP/SOC design and internal team for IP/SOC design issue debugging and root cause analysis.

Qualifications:

MS in EE/Communication/Computer Science

Good Knowledge of computer architecture, especially ARM CPU(Cortex A/M series), bus protocols(APB/AHB/AXI)

Good knowledge in  C language, and developing Custom UVM Agents and functional models in Verilog/System Verilog/UVM.

Experience in ASIC/SoC verification activities and should have participated in the successful completion of at least Ｏne ASIC/SoC project from Specifications to Silicon.

Experience in setting up and debugging functional and gate-level simulation

Experience of the design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.

High-speed Protocol Knowledge Ｏn DDR, PCIe, HDMI, MIPI, Ethernet, is an added advantage.

Nice to have knowledge of script language (ex. Perl/Python)

Self-motivation, flexibility, with strong interpersonal skills.

Effective communication skills, oral and written skills