soc design engineer数字前端设计

天津恩智浦强芯

岗位描述

SOC design Job Description:

As part of the SOC design team, engineer will mainly focus Ｏn following areas, but not limited to:

1. SoC design activities including top integration of various IP blocks, Clocking/Reset design, etc.

2. Micro-architecture of IP block with RTL coding/enhancements/area optimization/synthesis

3. Lint/CDC/Synthesis at block level.

4. Interact with PD/DFT/DV teams understand and resolve any issues and provide support as needed to build a high quality SoC

5. Debug and fixing of chip/IP level issues during SoC design or IP design phase

Job Requirement

1.Good knowledge of SoC design

2. Hands Ｏn experience with Verilog HDL is a must – familiarity with System Verilog is a plus

3. Solid background in digital logic is required

4. Familiarity with industry standard tools forLint/CDC/LEC/Simulations is required, familiarity with Synthesis/STA tools is plus

5. A good team player, open minded outlook towards work and a desire to learn new domains/technologies