公司信息
福田区槟榔道3号深港国际科技园E座4层409
数字芯片设计专家将负责高端ADC芯片设计的数字部分，希望该候选人具有包括前端设计及后端设计的经验。公司提供有竞争力的薪酬，研发目前具有挑战性的项目。
Qualifications
MPhil or PhD preferred with 10+ year of experience in high-performance digital or mixed-signal IC development in deep submicron CMOS processes
Must have a track record of mass production from initial designs
Must have 3GHz clock frequency logic design experience in mass production
Understanding of interface such as SPI, LVDS and JESD204B/C standards
Ability to work Ｏn both frontend and backend digital logic design
Must have tape-out experience in 28nm CMOS or FinFET process
Work independently according to schedules and be an active team pla
Contact: morrishe@caelustech.com ( Morris He )
