数字电路实现工程师

北京百瑞互联技术有限公司

福利待遇

五险一金 奖励计划 休假制度 法定节假日

岗位描述

Job Description

· Responsible for block/full-chip MCMM physical aware synthesis

· Responsible for UPF aware Formal Verification

· Responsible for RTL design to support DFT team 

· Responsible for SDC finalizing

· Responsible for timing ECO and signoff

· Responsible for UPF writing and VCLP check

· Responsible for power signoff 

· Co-work with physical design team for the best PPA

· Be a highly-valued member through excellent collaboration and teamwork with other teams

Qualifications

· BS degree or higher in EE, CE, or CS

· 2 years hands-on experience as DFT/Synthesis/STA engineers

· Familiar with Design Compiler, Formality, PrimeTime, VCLP

· Strong SDC writing and debugging experience

· Strong physical aware synthesis experience

· Strong timing ECO and STA signoff experience

· Strong Formal verification experience

· Good knowledge to UPF and low power check 

· Strong debugging and analytical skills

· English documents reading

· Good programming in Perl/Python, TCL and Shell programming

· Self-motivated, team work, and good communication skills