数字电路设计工程师

北京百瑞互联技术有限公司

福利待遇

五险一金 年终奖金 奖励计划 休假制度 法定节假日

岗位描述

Job Description

• Independent block and SoC RTL design and verification

• Analog and digital IP integration 

• RTL handoff quality check using EDA tools

• Prepare signoff quality full chip SDC file

• Prepare signoff quality full chip UPF file

• Support ASIC implementation

• Support FPGA prototyping

• Support DFT integration

• Support software and system production

• Write design documents

Qualifications

• 2 years hands-on experience in ASIC RTL design. Experience in Bluetooth, Mobile Computing or IoT is a plus

• Familiar with popular ASIC solutions (including specification and architecture)

• Familiar with ASIC design verification and implementation flow

• Familiar with relevant QA tools (for example Spyglass)

• Strong debugging and analytical skills, generate ideas, and provide innovative solutions to solve technical problems

• English documents reading

• Good programming in Perl/Python, TCL and Shell programming

• Self-motivated, team work, and good communication skills