数字后端工程师

1、   Work with the global design team to do complex SOC physical implementation for deep submicron design.
2、   Participates in block level backend design for complex SOC designs.
3、   Responsible for RTL to GDS flow including CPF definition, logic/physical synthesis, die size estimation, floor-planning, power planning, CTS, place and route, STA, signal integrity, timing closure, formal verification, DFM, DRC/LVS etc.
4、   Play a critical role in high performance design timing closure.