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soc design verification engineer数字验证 20000-40000 收藏 申请职位
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soc design verification engineer数字验证

20000-40000
天津-天津 -经济开发区
2021-08-09 更新 被浏览:
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赵伟
最近在线时间:2023-08-24 14:08
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招聘人数:若干 到岗时间:不限 年龄要求:不限 婚况要求:不限

Job Description

The position is responsible for developing verification plan, testcase, and verify the functionality MCU/MPU(Coretx-M/A) SOC and reporting the bugs in SOC or IP level.

Responsibilities: 

Verification plan development based On SOC spec, test case development and improvement to have better coverage and verification quality.

Ensure the complex SoC verification functional coverage and quality for SOC spec cross-check.

Work closely with backend and other function teams On power/timing analysis at gate level simulation.

Co-work with IP/SOC design and internal team for IP/SOC design issue debugging and root cause analysis.

Qualifications:

MS in EE/Communication/Computer Science

Good Knowledge of computer architecture, especially ARM CPU(Cortex A/M series), bus protocols(APB/AHB/AXI)

Good knowledge in  C language, and developing Custom UVM Agents and functional models in Verilog/System Verilog/UVM.

Experience in ASIC/SoC verification activities and should have participated in the successful completion of at least One ASIC/SoC project from Specifications to Silicon.

Experience in setting up and debugging functional and gate-level simulation

Experience of the design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.

High-speed Protocol Knowledge On DDR, PCIe, HDMI, MIPI, Ethernet, is an added advantage.

Nice to have knowledge of script language (ex. Perl/Python)

Self-motivation, flexibility, with strong interpersonal skills.

Effective communication skills, oral and written skills

求职提醒:求职过程请勿缴纳费用,谨防诈骗!若信息不实请举报。
该公司的其他职位
  • 芯片设计
  • 合资企业
  • 10-50人

NXP控股合资公司,地处天津泰达开发区的NXP SOC研发中心

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